1. Field of the Invention
This invention pertains generally to dynamic random access memory (DRAM) devices and, and more particularly to capacitorless DRAM memory cells.
2. Description of Related Art
The concept of a capacitorless DRAM cell was proposed to overcome scaling challenges for conventional 1-transistor/1-capacitor DRAM cells. The silicon-on-insulator (SOI) floating body cell (FBC) design was offered as a 4F2 cell (having a cell area of 4F2), but required more expensive SOI substrates, and was difficult to scale to very short channel lengths. The double-gate DRAM (DG-DRAM) cell was proposed as a more scalable design and was recently demonstrated at 70 nm gate length. However, the DG-RAM has a relatively large cell size (8F2), is susceptible to disturbance when incorporated within a memory array, and is not easily integrated into a conventional memory process flow.
Accordingly, a need exists for a capacitorless DRAM cell design which can attain very small channel lengths within a small (4F2) area and can be fabricated on low cost substrates using conventional techniques. These needs and others are met within the present invention, which overcomes the deficiencies of previously developed DRAM cell structures.